Memoryless nonlinearity in IT JL FinFET with spacer technology: Investigation towards reliability

Highlights

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Investigates the reliability issue of high-k spacer

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Effect of different temperature on the device analog/RF performance for Inverted ‘T' Junctionless FinFET

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The impact of spacer technology in ITJL FET

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Linearity and distortion analysis for the ITJL FinFET

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Temperature impact on characteristics to evaluate the compensation point

Abstract

This work investigates the reliability assessment of high-k spacer and the effect of temperature on the device analog/RF performance for Inverted ‘T' (IT) Junctionless (JL) FinFET. A systematic analysis is performed for different high-k spacer materials, like, SiO₂, Si₃N₄, and HfO₂ to improve the analog/RF performances. This work also represents the effect of oxide stacking i.e., low-k on high-k materials as a spacer to ensure device reliability for analog/RF performance. Various performances as subthreshold swing (SS), current switching ratio (I_ON/I_OFF ratio), drain induced barrier lowering (DIBL), transconductance (g_m), early voltage (V_EA), gain (A_V), higher order derivatives of current (g_m1, g_m2, g_m3), Capacitance (C_GS, C_GD, C_GG), cut-off frequency (f_T), 2nd and 3rd order voltage intercept point (VIP₂, VIP₃), 3rd order intermodulation input intercept point (IIP₃) are analyzed for the device. The obtained results are achieved with uniform high doping concentration under bulk conduction mechanism which downsizes the short channel effects and thereby enhances the linearity FoMs for analog/RF circuit applications. At 300 K, the acquire SCEs for high-k spacers, for example, SS, I_ON/I_OFF ratio, DIBL accomplish to be 64 mV/decade, 10⁷, 26 mV/V respectively. In contrast with distinctive temperature variation from 200 K to 400 K, the SCEs at 300 K are same to that of the high-k spacers.