Compare Efficiency of Different Multipliers Using Verilog Simulation & Modify an Efficient Multiplier

Abstract

Multipliers are the fundamental components in many digital signal processing systems. Many important signal processing systems are designed on VLSI platform as the integration growing rapidly. The signal processing systems & applications requires large computational capability, hence takes considerable amount of energy. In the VLSI system design performance, area and power consumption are three important parameters, of which power consumption is the gets prime importance. In today’s world, power consumption is very important factor. The largest contribution to the power consumption in multiplier is due to generation and reduction of partial products. So it is very much important to know the efficiency of different multipliers. This paper represents a detailed comparison between array multiplier, Wallace multiplier, Dadda multiplier, modified array multiplier on the basis of speed, area, power consumption using verilog simulation.